![]() ![]() The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM. Both memory blocks are 4-way associative with virtual index virtual tag (VIVT). The ARM core has separate 16KB of instruction and 16-KB data caches. The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-, 16-, or 8-bit data. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution. The AM1705 is a low-power ARM microprocessor based on an ARM926EJ-S. Commercial, Industrial, or Extended TemperatureĪll trademarks are the property of their respective owners. ![]() 176-Pin PowerPAD™ Plastic Quad Flat Pack, 0.5-mm Pin Pitch.Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules.Single-Shot Capture of up to Four Event Timestamps.Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs.Three 32-Bit Enhanced Capture (eCAP) Modules:.6 Single-Edge, 6 Dual-Edge Symmetric, or 3 Dual-Edge Asymmetric Outputs.Dedicated 16-Bit Time-Base Counter With Period and Frequency Control.Three Enhanced Pulse Width Modulators (eHRPWMs):.One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers).One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers).Six Clock Zones and 28 Serial Data Pins.Two Multichannel Audio Serial Ports (McASPs):.End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX.USB 2.0 OTG Port With Integrated PHY (USB0).Two Master and Slave Inter-Integrated Circuit (I 2C Bus™).Multimedia Card (MMC)/Secure Digital (SD) Card Interface With Secure Data I/O (SDIO).Entire Subsystem Under a Single PSC Clock Gating Domain.PRUSS can be Disabled Through Software to Save Power.Two Independent Programmable Real-Time Unit (PRU) Cores.Programmable Real-Time Unit Subsystem (PRUSS).Two Serial Peripheral Interfaces (SPIs) Each With One Chip Select. ![]()
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